• Static Timing Analysis (STA)
• Synthesis Signoff
• SerDes IP
• Timing Constraints
• ECO
• Low-Power Techniques

This senior role is responsible for driving static timing analysis and synthesis signoff for high-performance SerDes IPs. You will define timing methodologies, manage constraints, and ensure closure across multi-corner and multi-mode designs. The position requires close collaboration with RTL, DFT, and physical design teams. You will also mentor engineers and automate workflows using scripting. Deep expertise in STA tools, timing ECOs, and low-power techniques is required.