• STA Lead
• Static Timing Analysis
• PrimeTime
• Timing ECO
• CPU/APU Design
• Critical Path Optimization

This senior role leads static timing analysis for high-frequency CPU and APU designs. You will drive timing closure across multiple process corners and advanced technology nodes. The position involves developing timing constraints, performing ECOs, and optimizing critical paths. You will collaborate closely with RTL, physical design, and verification teams. Deep expertise in PrimeTime, STA methodologies, and yield-aware timing analysis is required.