• SerDes
• UVM
• Testbench Development
• Signal Integrity
• Jitter/BER Analysis
• Protocol Compliance
• High-speed IO

This role is responsible for verification of high-speed SerDes IPs and subsystems. You will develop UVM-based testbenches, execute simulations, and debug protocol and signal integrity issues. The position includes validating performance metrics such as jitter, BER, and eye diagrams. You will collaborate closely with design and hardware teams to ensure protocol compliance. Strong verification and debugging expertise is essential.