IP Design Verification ⭐ Featured

• Security IP
• UVM
• SystemVerilog
• Verification Architecture
• Coverage Analysis
• Mentoring
• Scripting

This role focuses on block and subsystem level verification of security-related IPs used across AMD SoCs. You will design verification architectures, develop UVM-based testbenches, and drive verification closure. The position involves debugging regressions, analyzing coverage, and collaborating with design teams. You may also provide technical leadership and mentorship at advanced levels. Strong SystemVerilog, UVM, and scripting skills are required.