• RTL Design
• UPF (Unified Power Format)
• CDC (Clock Domain Crossing)
• Low-power Verification
• Lint
• Static Analysis
• FPGA

This role contributes to RTL design quality and front-end methodology for next-generation FPGA and SoC products. You will improve RTL and low-power verification flows using UPF and static analysis tools. The position involves enhancing lint, CDC, equivalence, and power-domain verification methodologies. You will collaborate with design teams to ensure robust multi-power-domain architectures. Strong RTL design and UPF expertise are required.