• SDC (Synopsys Design Constraints)
• Static Timing Analysis (STA)
• Timing Convergence
• Noise Analysis
• OCV
• IR-drop

This role focuses on static timing capture and constraint development for high-performance SoC and IP designs. You will own SDC creation, multi-corner timing analysis, and timing convergence activities. The position involves close collaboration with RTL, physical design, and methodology teams. You will debug complex timing issues including noise, OCV, and IR-drop effects. Strong expertise in STA tools and scripting is required.