Lead IP Design Verification Engineer ⭐ Featured

• Design Verification Lead
• SystemVerilog
• UVM
• Verification Sign-off
• ASIC Lifecycle
• Stakeholder Management

This role leads IP-level verification efforts from planning through sign-off. You will own complex verification scopes, mentor engineers, and manage execution risks and dependencies. The position involves deep hands-on work with SystemVerilog and UVM, as well as stakeholder communication. You will drive verification quality, efficiency, and closure across projects. Strong verification leadership and full-cycle ASIC experience are essential.