Design Verification Engineer New

• Design Verification
• UVM
• SystemVerilog
• RTL
• VHDL
• Verilog
• Constrained-Random Verification
• Coverage-Driven Verification
• Testbench Development
• Simulation
• Debugging
• ASIC Design
• Scripting (Python/Perl)

As a Design Verification Engineer at Broadcom, you will be responsible for verifying complex semiconductor and chip designs to ensure functional correctness and performance compliance. Your role involves developing and executing verification plans, building testbenches using industry-standard methodologies such as UVM, and writing directed and constrained-random test cases. You will work closely with design engineers to understand RTL implementations, identify potential issues, and drive verification closure through coverage-driven techniques. Additionally, you will debug simulation failures, analyze waveforms, and contribute to improving verification processes and methodologies across the team.