Lead Physical Design, Physical Implementation, STA ⭐ Featured
AMD
This role leads physical design execution from RTL to GDSII for high-performance server SoCs. You will own floorplanning, placement, CTS, routing, ext...
Opportunities from AMD across 2 locations and 1 company — updated with verified listings.
Showing 1 to 12 of 21 jobs
This role leads physical design execution from RTL to GDSII for high-performance server SoCs. You will own floorplanning, placement, CTS, routing, ext...
This role focuses on system-level validation and compliance of high-speed IO interfaces across AMD SoCs. You will define and execute electrical, proto...
This role leads SoC RTL design activities with a focus on clocking, reset, and boot architecture across AMD platforms. You will work closely with SoC ...
This role focuses on front-end implementation including synthesis, timing closure, CDC, lint, and DFX for high-speed processor designs. You will defin...
This role leads full-chip physical design with a strong focus on power convergence and sign-off. You will oversee RTL-to-GDS execution, low-power impl...
This leadership role owns post-silicon validation strategy and execution across multiple IP domains including cores, memory, HSIO, and power managemen...
This role leads DFT architecture and implementation across AMD products from design to production. You will oversee scan, MBIST, IJTAG, and ATPG strat...
This role focuses on CPU workload analysis, benchmarking, and microarchitectural performance evaluation. You will analyze silicon behavior using traci...
This role focuses on static timing capture and constraint development for high-performance SoC and IP designs. You will own SDC creation, multi-corner...
This senior role leads end-to-end SoC development for high-speed networking silicon targeting data center and AI markets. You will define architecture...
This role focuses on post-silicon system and silicon debug for AMD embedded CPU and APU platforms. You will lead debug and triage activities to isolat...
This role contributes to RTL design quality and front-end methodology for next-generation FPGA and SoC products. You will improve RTL and low-power ve...