Sr. Verification Engineer

As a Senior Verification Engineer at Broadcom, you will be responsible for developing and executing verification plans for complex semiconductor designs. You will create testbenches using industry-standard methodologies such as UVM to verify RTL designs and ensure functional correctness. Your role will involve writing directed and constrained-random tests, developing coverage models, and performing coverage-driven verification to achieve comprehensive design validation. You will collaborate closely with design engineers to understand specifications, identify corner cases, and debug failures. Additionally, you will be expected to mentor junior engineers, drive verification closure, and contribute to improving verification processes and methodologies across the team.