IP DFT Verification Engineer

As an IP DFT Verification Engineer at Broadcom, you will focus on verifying Design-for-Test (DFT) logic at the IP level for complex semiconductor products. You will develop and execute DFT verification plans covering scan insertion, ATPG, BIST (memory and logic), JTAG/boundary scan, and other testability features. Your responsibilities include creating testbenches to validate DFT functionality, running fault simulations, and ensuring DFT structures meet manufacturing test requirements. You will work closely with DFT implementation engineers and design teams to understand DFT architectures, debug issues in simulation, and verify proper integration of DFT features. You will also contribute to improving DFT verification flows and methodologies to enhance efficiency and coverage.